Auto-tuning Fault Tolerance Technique for DSP-Based Circuits in Transportation Systems

As new technologies use a reduced transistor size to improve performance, circuits are becoming remarkably sensitive to soft errors that become a serious threat for critical applications reliability. Most of the existing reliability enhancing techniques lead to costly hardware. The masking phenomenon is fundamental to accurately estimating soft error rates (SER). The first contribution of this paper is a new crosslayer model for input-dependent Single Event Transient (SET) masking mechanisms combining Transistor Level Masking (TLM) and System Level Masking (SLM). We, secondly, use this model to build an autotuning fault tolerant circuit dedicated to obstacle detection systems in railway transportation. Based on our input-dependent masking model, the proposed architecture evaluates the effective circuit’s vulnerability at runtime and accordingly adapts the reliability boosting strategy, leading to a reliable circuit with optimized overheads. When compared to the Triple Modular Redundancy, our technique reduces the number of FPGA LUTs (resp. DSP slices) by up to 45% (resp. 33%).